[1] 钱利波, 朱樟明, 杨银堂. 一种考虑硅通孔电阻-电容效应的三维互连线模型[J]. 物理学报, 2012, 61(6):068001. [2] 许川佩, 陈家栋, 万春霆. 基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究[J]. 电子与信息学报, 2015, 37(2):477-483 [3] MOORE G E. Cramming more components onto integrated circuits[J]. Cramming More Components onto Integrated Circuits, 1998, 86(1):82-85. [4] 朱樟明, 左平, 杨银堂. 考虑硅通孔的三维集成电路热传输解析模型[J].物理学报,2011, 60(11):118001. [5] CALEB S, ANKUR S. TSV replacement and shield insertion for TSV-TSV coupling reduction in 3-D global placement[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2015, 34(4):554-562. [6] YARUI P, TAIGON S, DUSAN P, et al. Silicon effect-aware full-chip extraction and mitigation of TSV-to-TSV coupling[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014, 33(12):1900-1913. [7] WANG F J, YANG Y T, ZHU ZH M, et al. Temperature characteristics of three-dimensional chip-multiprocessors[J]. Chinese Journal of Computational Physics, 2012, 29(6):938-942. [8] WANG F J, ZHU ZH M, YANG Y T, et al. A thermal model for top layer of three-dimensional integrated circuits with through silicon via[J]. Chinese Journal of Computational Physics, 2012, 29(4):580-584. [9] ZHANG Y,DONG G,YANG Y T, et al.Thermal management of 3D integrated circuits considering horizontal heat transfer effect[J]. Chinese Journal of Computational Physics, 2013, 30(5):753-758. [10] HAN K J, SWAMINATHAN M, BANDYOPADHYAY T. Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions[J]. IEEE Transactions on Advanced Packaging, 2010.33(4):804-817. [11] HAN K J, SWAMINATHAN M, JEONG J. Modeling of through-silicon via (TSV) interposer considering depletion capacitance and substrate layer thickness effects[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2015, 5(1):108-118. [12] FENG W, WATANABE N, SHIMAMOTO H, et al. Analysis of thermal stress distribution for TSV with novel structure[C]. 3D Systems Integration Conference (3DIC), 2014:1-4. [13] LU Tiantao, SRIVASTAVA A. Modeling and layout optimization for tapered TSVs[J]. IEEE Transactions on Very Large Scale Integration Systems, 2015,23(12):3129-3132. [14] SU J R, WANG F, ZHANG W M. Capacitance expressions and electrical characterization of tapered through-silicon-vias for 3-D ICs[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2015, 5(10):1488-1496. [15] YIN X K,ZHU Z M,YANG Y T,et al. Metal proportion optimization of annular through-silicon via considering temperature and keep-out zone[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2015, 5(8):1093-1099. [16] CHEN A B, LIANG F, WANG G F, et al. Closed-form impedance model for annular through-silicon via pairs in three-dimensional integration[J]. IET Microwaves, Antennas & Propagation,2015, 9(8):808-813. [17] WANG F J, ZHU Z M, YANG Y T, et al. An effective approach of reducing the keep-out-zone induced by coaxial through-silicon-via[J]. IEEE Transactions on Electron Devices,2014, 61(8):2928-2934. [18] DANIEL H J, HEEGON K, SUKJIN K, et al.30 Gbps high-speed characterization and channel performance of coaxial through silicon via[J]. IEEE Microwave and Wireless Components Letters,2014, 24(11):814-816. [19] WANG F J, YU N M. Study on thermal stress and keep-out zone induced by Cu and SiO2 filled coaxial-annular through-silicon via[J]. IEICE Electronics Express, 2015, 12(22):142-148. [20] WANG W, ZHANG L, LI N, et al. Quantum transport in hetero-material-gate CNTFETs with gate underlap:A numerical study[J]. Chinese Journal of Computational Physics, 2015, 32(2):229-239. [21] POZAR D M. 张肇议,周乐柱,等. 微波工程[M].3版.北京:电子工业出版社,2015:45-47. [22] LIANG Y P, DING X, CHEN Y Q, et al. Application of scaled boundary finite element method in electromagnetic field problems[J]. Chinese Journal of Computational Physics, 2017, 34(2):205-213. |