Abstract: A three-dimensional analytical heat transfer model for stacked chips is developed, which takes into account horizontal heat transfer effect in three-dimensional integrated circuits (3D ICs) with through silicon via (TSV). Effects of horizontal heat transfer is analyzed with number of strata, TSV density, TSV diameter and thickness of BEOL layer under specific process and thermal parameters. It indicated that temperature rise simulated by the model is lower compared with result not considering horizontal heat transfer effect. Difference of temperature rise can be above 10%. Effect of horizontal heat transfer on thermal management of 3D ICs is more obvious with increasing of integrated level. The model conforms to actual situation. It is more accurate in analyzing temperatures of stacked chips in 3D ICs.

Key words: 3D IC, thermal management, through silicon via, horizontal thermal diffusion effect