考虑硅通孔的三维集成电路最高层温度模型

计算物理 ›› 2012, Vol. 29 ›› Issue (4): 580-584.

考虑硅通孔的三维集成电路最高层温度模型

王凤娟, 朱樟明, 杨银堂, 王宁

西安电子科技大学微电子学院, 陕西西安, 710071

收稿日期:2011-08-29 修回日期:2011-12-03 出版日期:2012-09-25 发布日期:2012-09-25
作者简介:王凤娟(1985-),女,博士生,主要从事三维集成电路热管理及电参数模型研究,E-mail:cicy4@hotmail.com
基金资助:
国家自然科学基金(60725415,60971066,61006028);国家863计划(2009AA01Z258);陕西省重大技术创新专项(2009ZKC02-11)资助项目

A Thermal Model for Top Layer of Three-dimensional Integrated Circuits with Through Silicon Via

WANG Fengjuan, ZHU Zhangming, YANG Yintang, WANG Ning

School of Microelectronics, Xidian University, Xi'an 710071, China

Received:2011-08-29 Revised:2011-12-03 Online:2012-09-25 Published:2012-09-25

摘要/Abstract

摘要： 针对三维集成电路最高层芯片,引入硅通孔面积比例因子r,提出了考虑硅通孔的温度解析模型.Matlab分析表明,在芯片堆叠层数及芯片工作状态相同的情况下,考虑硅通孔之后的芯片温度比未考虑硅通孔时要低;r越大,芯片温度越低;当芯片堆叠层数较多且r较小时,温度随着r的减小急剧上升;对于8层的三维集成电路,硅通孔面积比例因子的最佳范围为0.5%~1%.

关键词: 三维集成电路, 硅通孔, 温度模型, 最高层芯片, 热管理

Abstract: With through silicon via(TSV) area scale factor r,an analytical thermal model for top layer of three-dimensional integrated circuits(3D IC) taking TSV into account was proposed.It is shown that temperature is lower after considering TSVs under same working conditions;the greater the scale factor r,the lower the temperature is;For more layers and smaller r,temperature increases sharply with decrease of r;The best range of TSV area ratio factor r is 0.5% to 1% for an 8-layer 3D IC.

Key words: three-dimensional integrated circuit, through silicon via, thermal model, top layer, thermal management

中图分类号:

TN402

王凤娟, 朱樟明, 杨银堂, 王宁. 考虑硅通孔的三维集成电路最高层温度模型[J]. 计算物理, 2012, 29(4): 580-584.

WANG Fengjuan, ZHU Zhangming, YANG Yintang, WANG Ning. A Thermal Model for Top Layer of Three-dimensional Integrated Circuits with Through Silicon Via[J]. CHINESE JOURNAL OF COMPUTATIONAL PHYSICS, 2012, 29(4): 580-584.

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