For coaxial-annular through silicon vias (CA-TSV) structure with superior performances, characteristic impedance, power, time constant and analytical models of parasitic parameters are proposed and effects of structural parameters on electrical properties are studied. S21 parameter was verified by software HFSS. It shows that increasing inner diameter of CA-TSV or reducing outer diameter reduces characteristic impedance, while reducing inner diameter of CA-TSV or increasing outer diameter reduces its power consumption effectively. Increasing inner diameter of CA-TSV or outer diameter reduces time constant of RC equivalent circuit, whereas increasing inner diameter of CA-TSV or reducing outer diameter reduces time constant of RL equivalent circuit. Increasing inner diameter of CA-TSV or outer diameter reduces resistance effectively and capacitance can be increased significantly. It provides reference for electrical properties of three-dimensional integrated circuits based on TSV interconnects.

An expression of thermal resistance matrix is given.Transient temperature characteristics of three-dimensional chip-muhiprocessors(3D-CMP) are studied.Effect of heat capacity,thermal resistance and power consumption on temperature is analyzed. It shows that steady temperature of 3D-CMP is limited effectively by reducing thermal resistance and power consumption.Heat capacity influences rise time of temperature.It does not affect steady temperature.

With through silicon via(TSV) area scale factor r,an analytical thermal model for top layer of three-dimensional integrated circuits(3D IC) taking TSV into account was proposed.It is shown that temperature is lower after considering TSVs under same working conditions;the greater the scale factor r,the lower the temperature is;For more layers and smaller r,temperature increases sharply with decrease of r;The best range of TSV area ratio factor r is 0.5% to 1% for an 8-layer 3D IC.

With consideration of via effect and heat fringing effect, a thermoelectric simulation method is proposed which modifies node heat flow due to temperature distribution. Based on thermoelectric duality, thermal resistance models including inner/inter-layer and vias are presented. Take advantage of feedback relationship between heat and electric, the node network heat flow model is modified with temperature distribution. Multilevel interconnects temperature distribution with polymer and silicon oxide as insulator dielectric are analyzed. Compared with results of finite element, the relative standards deviation of the proposed method can be reduced by 71.2% and 12. 9% respectively than those of available models. With consideration of via effect and heat fringing effect, we calculate peak temperature rise in different technology nodes. It shows that interconnect temperature distribution is overestimated in traditional models.