Weighted Laguerre polynomials-finite difference time domain (WLP-FDTD) method is employed to analyze transient response of transmission line in high-speed interconnect circuit system. Based on telegraph equation in equivalent circuit networks model,current and voltage are computed with weighted Laguerre polynomials. According to orthogonality,stability condition is eliminated. Different from finite difference time domain method,WLP-FDTD method is unconditional stable,which separates time and space variables. It is fast in computing large number of dissection networks for a transmission line. It shows that WLP-FDTD method is more efficient than traditional FDTD in analysis of transmission line. At last,a program with GUI is developed.

A three-dimensional analytical heat transfer model for stacked chips is developed, which takes into account horizontal heat transfer effect in three-dimensional integrated circuits (3D ICs) with through silicon via (TSV). Effects of horizontal heat transfer is analyzed with number of strata, TSV density, TSV diameter and thickness of BEOL layer under specific process and thermal parameters. It indicated that temperature rise simulated by the model is lower compared with result not considering horizontal heat transfer effect. Difference of temperature rise can be above 10%. Effect of horizontal heat transfer on thermal management of 3D ICs is more obvious with increasing of integrated level. The model conforms to actual situation. It is more accurate in analyzing temperatures of stacked chips in 3D ICs.

An expression of thermal resistance matrix is given.Transient temperature characteristics of three-dimensional chip-muhiprocessors(3D-CMP) are studied.Effect of heat capacity,thermal resistance and power consumption on temperature is analyzed. It shows that steady temperature of 3D-CMP is limited effectively by reducing thermal resistance and power consumption.Heat capacity influences rise time of temperature.It does not affect steady temperature.

With through silicon via(TSV) area scale factor r,an analytical thermal model for top layer of three-dimensional integrated circuits(3D IC) taking TSV into account was proposed.It is shown that temperature is lower after considering TSVs under same working conditions;the greater the scale factor r,the lower the temperature is;For more layers and smaller r,temperature increases sharply with decrease of r;The best range of TSV area ratio factor r is 0.5% to 1% for an 8-layer 3D IC.

With consideration of via effect and heat fringing effect, a thermoelectric simulation method is proposed which modifies node heat flow due to temperature distribution. Based on thermoelectric duality, thermal resistance models including inner/inter-layer and vias are presented. Take advantage of feedback relationship between heat and electric, the node network heat flow model is modified with temperature distribution. Multilevel interconnects temperature distribution with polymer and silicon oxide as insulator dielectric are analyzed. Compared with results of finite element, the relative standards deviation of the proposed method can be reduced by 71.2% and 12. 9% respectively than those of available models. With consideration of via effect and heat fringing effect, we calculate peak temperature rise in different technology nodes. It shows that interconnect temperature distribution is overestimated in traditional models.

A method with a set of improved basis functions in vaouum-jellium region for Film-LAPW, method suited to jellium/slab model is proposed. The calculations for examination of this method, with three layers of W slab to simulate the W(100) surface covered with Cs overlayer is made. The results are more stabilized and accurate, and are much closer to experiments. The contribution weights of each vaccum basis function to the wave function is analysed.