Based on interconnection transmission differential equation,transform voltage and current expressions are derived by incorporating appropriate boundary conditions for interconnect energy analysis.We considered a practical transmission line with driver and load to find out relation between transform input and output voltage and current responses.Interconnection energy distribution is obtained,which considers non-ideal step stimulation.In 65 nm CMOS process,the non-uniform interconnect analytic model enables to estimate energy within 5% compared with Hspice simulations.The method has high accuracy.The analytic model can be applied to front end optimizing design and analysis of high performance global interconnection.

A three-dimensional analytical heat transfer model for stacked chips is developed, which takes into account horizontal heat transfer effect in three-dimensional integrated circuits (3D ICs) with through silicon via (TSV). Effects of horizontal heat transfer is analyzed with number of strata, TSV density, TSV diameter and thickness of BEOL layer under specific process and thermal parameters. It indicated that temperature rise simulated by the model is lower compared with result not considering horizontal heat transfer effect. Difference of temperature rise can be above 10%. Effect of horizontal heat transfer on thermal management of 3D ICs is more obvious with increasing of integrated level. The model conforms to actual situation. It is more accurate in analyzing temperatures of stacked chips in 3D ICs.

An expression of thermal resistance matrix is given.Transient temperature characteristics of three-dimensional chip-muhiprocessors(3D-CMP) are studied.Effect of heat capacity,thermal resistance and power consumption on temperature is analyzed. It shows that steady temperature of 3D-CMP is limited effectively by reducing thermal resistance and power consumption.Heat capacity influences rise time of temperature.It does not affect steady temperature.

With through silicon via(TSV) area scale factor r,an analytical thermal model for top layer of three-dimensional integrated circuits(3D IC) taking TSV into account was proposed.It is shown that temperature is lower after considering TSVs under same working conditions;the greater the scale factor r,the lower the temperature is;For more layers and smaller r,temperature increases sharply with decrease of r;The best range of TSV area ratio factor r is 0.5% to 1% for an 8-layer 3D IC.

With consideration of via effect and heat fringing effect, a thermoelectric simulation method is proposed which modifies node heat flow due to temperature distribution. Based on thermoelectric duality, thermal resistance models including inner/inter-layer and vias are presented. Take advantage of feedback relationship between heat and electric, the node network heat flow model is modified with temperature distribution. Multilevel interconnects temperature distribution with polymer and silicon oxide as insulator dielectric are analyzed. Compared with results of finite element, the relative standards deviation of the proposed method can be reduced by 71.2% and 12. 9% respectively than those of available models. With consideration of via effect and heat fringing effect, we calculate peak temperature rise in different technology nodes. It shows that interconnect temperature distribution is overestimated in traditional models.

With influences of interconnect inductance,thermal-electric coupling effects and interconnect temperature distribution,a delay optimized method by repeater insertion is presented.A interconnect resistance model and a delay model are obtained respectively based on interconnect temperature distribution.The repeater insertion optimal delay is calculated considering electro-thermal coupling among power,delay and temperature.Optimized results are successfully obtained with Matlab software.Repeater insertion in 45 nm technology is simulated.It shows effectiveness of the method.In addition,it indicates that the optimal delay is overestimated without inductance effect.Optimal delay is underestimated without consideration of temperature distribution.As overestimated global interconnect width is 245nm,8.71% optimal delay can be underestimated without considering temperature distribution effect.

With analysis on internal carrier transport mechanism in silicon carbide(SiC),an improved analytical model for dc current voltage and small signal parameters of 4H-SiC metal-semiconductor field effect transistor(MESFET) is proposed considering carrier velocity saturation and charge controlling.Incomplete dopant ionization and parasitic drain-source resistances are considered simultaneously.The simulated maximum transconductance is 48 mS·mm^-1 at a gate voltage of 0 V.Simulations and physical measurements show good agreement.The model is simple in calculation and distinct in physical mechanism.It is suitable for design and research of SiC devices and circuits.

Structure and electronic properties of silicon carbide nanotube(SiCNT) with and without adsorption of NO₂ are calculated with CASTEP package based on density functional theory.A stable adsorption between nanotube and gas molecule is formed and conductivity of the SiCNT is improved obviously.It is shown that SiCNT is a potential candidate for gas sensors.It is expected to provide a useful guidance in developing SiCNT-based sensors for NO₂ molecules.